Description
Triconex 3101S2 Main Processor Module
Product Overview
The Triconex 3101S2 is the Main Processor (MP) module used in the Triconex Tri-GP General Purpose controller. It is the central computing element of one channel within the system’s Triple-Modular Redundant architecture. A complete Tri-GP controller uses three 3101S2 modules operating in parallel, with each processor communicating with the other two through the fault-tolerant TriBus. The processors execute the application, exchange input and output data, perform voting, and coordinate the I/O processing associated with their respective channels.
The processor architecture documented for the 3101S2 uses a Motorola MPC860 32-bit processor at 50 MHz, with 6 MB of flash storage, 16 MB of DRAM for application execution and program/SOE data, and 8 KB of CRC-protected NVRAM for retentive variables. The module also contains a dedicated I/O processor based on the MPC860 architecture, with 16 MB of DRAM and shared memory for communication with the control processor.
For an existing Tri-GP installation, the Triconex 3101S2 is not interchangeable with the 3201S2 communication module or any Tricon/Trident processor simply because the modules perform high-level control functions. The 3101S2 belongs specifically to the Tri-GP MP architecture and uses the 2101S2 Main Processor Baseplate. Its ports and buses are also part of the Tri-GP system design: Ethernet is provided for TriStation 1131 programming/diagnostics, an RS-232/RS-485 Modbus port is available on the baseplate, and the processor participates in the 2 Mbps I/O bus and 25 Mbps TriBus architecture.
Product Introduction
When a Tri-GP controller loses a main processor channel, the issue is not simply a PLC CPU replacement. The 3101S2 participates directly in the system’s TMR voting, TriBus synchronization, I/O processing, diagnostics, and application execution. The system is designed around three MP modules, rather than a single central CPU.
For legacy Tri-GP replacement, the 3101S2 must therefore be evaluated as part of the complete processor set and 2101S2 baseplate arrangement. Firmware, controller configuration, processor health, battery condition, and the relationship between the three MP channels all matter during commissioning.
Key Technical Specifications
| Parameter | Value |
|---|---|
| Product Model | 3101S2 |
| Manufacturer / Brand | Triconex / Invensys |
| Product Series | Tri-GP General Purpose |
| Product Type | Main Processor Module |
| System Architecture | Triple-Modular Redundant (TMR) |
| Required MP Modules | 3 per Tri-GP controller |
| Control Processor | Motorola MPC860, 32-bit |
| Control Processor Speed | 50 MHz |
| Control Program Flash | 6 MB, CRC-protected |
| Control Program DRAM | 16 MB, byte parity |
| NVRAM | 8 KB, CRC-protected |
| NVRAM Function | Retentive variables |
| I/O Processor | Motorola MPC860, 32-bit, 50 MHz |
| I/O Processor DRAM | 16 MB, byte parity |
| Shared Memory | 128 KB |
| TriBus | 25 Mbps, CRC-protected, 32-bit + parity DMA |
| I/O Bus | RS-485, 2 Mbps HDLC |
| TriStation Port | 10BaseT Ethernet, RJ-45 |
| Modbus Port | RS-232/RS-485 DTE, DB-9 |
| Debug Port | RJ-12 |
| Alarm Contacts | Redundant, normally closed |
| Logic Power | 8 W maximum |
| Main Processor Baseplate | 2101S2 |
| Standard TriPak | 5101S2 |
The processor and memory specifications above are documented in the Tri-GP planning/installation material; the later Tri-GP technical guide also lists 3101S2 with an 8 W maximum logic-power requirement.
Major Features / Practical Advantages
TMR Main Processor Architecture
The 3101S2 is one channel of a three-processor control architecture. Each MP operates in parallel with the other two, and the processors exchange information through TriBus. This is fundamental to how Tri-GP maintains fault tolerance: the system does not depend on a single CPU executing the application.
That distinction is important during troubleshooting. A processor alarm does not automatically mean that the entire controller has stopped executing. The architecture is specifically designed to detect channel faults and maintain operation using the remaining healthy channels.
3101S2
Motorola MPC860 Processing
The documented control processor is a Motorola MPC860, 32-bit, 50 MHz device. The same processor family is used for the dedicated I/O processor. The control processor executes the application while the I/O processor manages communication between the MP and I/O modules.
This division reduces the need for the application processor to directly manage every I/O transaction. The I/O processor maintains the communication path to the field I/O architecture while the main processor handles application execution and system-level coordination.
6 MB Flash Storage
The 3101S2 contains 6 MB of CRC-protected flash for the SX, I/O processor, and control application storage. Application code is loaded into DRAM for execution.
For legacy procurement, this means that processor compatibility should not be evaluated solely from the external model number. The installed software/firmware environment and TriStation configuration are equally important.
16 MB DRAM for Application Execution
The control processor has 16 MB of DRAM used for control-application execution, program data, and Sequence-of-Events information. A second 16 MB DRAM area is assigned to the I/O processor.
This memory is volatile operating memory, while the separate NVRAM provides retention for critical variables. The distinction is useful when evaluating processor failures or power-loss behavior.
Battery-Backed NVRAM
The module provides 8 KB of CRC-protected NVRAM for retentive variables. The planning guide identifies a ½-AA lithium battery with a predicted 15-year life.
This is one area where an old spare deserves closer inspection. A processor that has been sitting in inventory for many years may still be electrically functional while having a battery approaching the end of its expected service life.
TriBus Communication
The three MP modules communicate over the TriBus, documented at 25 Mbps with CRC-protected 32-bit plus parity DMA. This high-speed processor-to-processor path supports synchronization and exchange of control information required by the TMR architecture.
A TriBus-related fault should not be confused with a normal Ethernet or Modbus communication failure. These interfaces serve different purposes within the Tri-GP architecture.
Dedicated I/O Processor
Each 3101S2 contains an I/O processor that manages communication between the MP and the field I/O modules. The documented I/O processor uses an , 16 MB DRAM, 128 KB shared memory, and a 2 Mbps HDLC diagnostic bus.
This is why the 3101S2 is more than a simple application CPU. It is responsible for coordinating the processor’s channel-level relationship with the Tri-GP I/O system.
Ethernet and Modbus Interfaces
The MP provides a 10BaseT Ethernet RJ-45 connection used for TriStation 1131 programming and diagnostic access. A separate RS-232/RS-485 DTE DB-9 Modbus port supports Modbus communications.
The Ethernet port should not be casually treated as a general-purpose plant Ethernet interface. Its documented role includes TriStation 1131 communication, firmware/application transfer, and diagnostics.
Redundant Power Inputs
The Main Processor receives power from redundant 24 VDC sources. The Tri-GP architecture is designed so that loss of one external power source does not by itself interrupt controller performance. Critical retentive data is maintained in NVRAM.
This makes the processor’s power-input arrangement an important part of system troubleshooting. A replacement MP should be evaluated together with the 2101S2 baseplate and redundant power wiring.
Online Maintenance Architecture
Tri-GP documentation describes a hot-spare MP arrangement: each I/O baseplate supports two MP modules in one logical slot, allowing active and hot-spare processors to receive the same field information. The MPs switch control between the two healthy I/O modules on a periodic basis so diagnostics can be performed.
That supports online maintenance strategies, but it should not be interpreted as a blanket authorization to remove any 3101S2 under live conditions. The actual replacement procedure must follow the installed system’s approved maintenance documentation.
Related Products
- 2101S2 — Main Processor Baseplate for the 3101S2. It provides the physical and electrical interface for the Tri-GP MP modules.
- 5101S2 — Main Processor TriPak consisting of three 3101S2 modules and one 2101S2 Main Processor Baseplate Kit.
- 3201S2 — Tri-GP Communication Module. It handles external communication functions and is not a replacement for the 3101S2 processor.
- 2201S2 — Communication Module Baseplate used with the 3201S2.
- 3211S2 — Communications Integration Module used for expanded communication integration in Tri-GP systems.
- 3351S2 — 32-point TMR analog input module for 4–20 mA process signals.
- 3301S2 — 32-point-class Tri-GP digital input module for discrete field signals.
- 3311S2 — High-resolution Tri-GP digital input module.
- 3481S2 — Four-point TMR analog output module.
- 3401S2 — Tri-GP digital output module.
- 3382S2 — Enhanced pulse-input module for frequency/pulse measurement applications.
FAQ
Is the 3101S2 the CPU of a Tri-GP system?
Yes. More precisely, it is the Main Processor Module and forms one of the three processing channels in the Tri-GP TMR controller. A complete controller uses three MP modules operating in parallel.
Can I replace one 3101S2 while the system is running?
The Tri-GP architecture supports an active/hot-spare MP arrangement, and the documentation describes online module repair. However, the actual replacement must follow the approved maintenance procedure for the installed system. Do not treat the presence of a spare processor slot as permission for uncontrolled live removal.
What baseplate does the 3101S2 use?
The documented MP baseplate is the 2101S2. The standard 5101S2 Main Processor TriPak consists of three 3101S2 modules and one 2101S2 baseplate kit.
Does the 3101S2 use Ethernet?
Yes. The documented MP architecture provides one 10BaseT Ethernet RJ-45 connection. It is used for TriStation 1131 programming and diagnostic communication and can also be involved in firmware/application transfer.
Does the 3101S2 support Modbus?
Yes. The MP provides one RS-232/RS-485 DTE Modbus port through a DB-9 connection. The documented MP communication capability is Modbus slave; expanded master/slave and additional Ethernet capabilities are available through the CIM/CM architecture.
Does this support firmware v3.1?
The 3101S2 model number alone does not establish firmware v3.1 compatibility. The Tri-GP documentation covers different system generations, and firmware/software compatibility needs to be checked against the installed Tri-GP controller, TriStation environment, and existing processor configuration.
How much memory does the 3101S2 have?
The documented control processor section specifies 6 MB flash, 16 MB DRAM, and 8 KB NVRAM. The dedicated I/O processor has another 16 MB DRAM plus 128 KB shared memory.
Does the 3101S2 retain the control program after power loss?
The control application is stored in flash and loaded into DRAM for execution. The 8 KB NVRAM is used for retentive variables rather than serving as the primary application-program storage.
Is 3101S2 interchangeable with a Tricon main processor?
No. The 3101S2 is specifically identified as the Tri-GP Main Processor Module and uses the Tri-GP 2101S2 baseplate and associated TriBus/I/O architecture. A similarly numbered or similarly described Tricon-family processor should not be substituted without documented system compatibility.
What is the logic power requirement?
The Tri-GP technical guide lists 8 W maximum logic power for the 3101S2. Field power is not applicable to the MP in the same way it is to field I/O modules.
Procurement Note
For a Triconex 3101S2 replacement, the most important mistake to avoid is treating the part number as a standalone PLC CPU. It is one processor channel in a three-MP Tri-GP architecture. Verify the existing 2101S2 baseplate, Tri-GP system generation, firmware/software environment, processor configuration, TriBus condition, redundant 24 VDC power arrangement, and battery status before installation.
For a spare unit, inspect the actual nameplate and connector condition rather than relying only on a supplier’s description. The published documentation identifies the 3101S2 as a Tri-GP MP and the standard 5101S2 assembly as three 3101S2 modules plus the 2101S2 baseplate.
Battery age deserves particular attention on old inventory. The planning guide specifies a ½-AA lithium battery with a predicted 15-year life and explicitly warns about the hazards associated with incorrect battery replacement. That is a maintenance issue worth resolving before the processor becomes a critical installed spare.
When sourcing legacy hardware, identify whether the unit is new surplus, previously installed, or refurbished, and request the complete model marking and revision information. For a safety controller, a visually clean processor is not enough evidence of configuration compatibility or functional condition.
